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CY62126ESL MoBL(R)
1-Mbit (64K x 16) Static RAM
Features

Very high speed: 45 ns Wide voltage range: 2.2V-3.6V and 4.5V-5.5V Ultra low standby power Typical standby current: 1 A Maximum standby current: 4 A Ultra low active power Typical active current: 1.3 mA at f = 1 MHz Easy memory expansion with CE, and OE features Automatic power down when deselected CMOS for optimum speed and power Available in Pb-free 44-Pin TSOP II package
consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99 percent when deselected (CE HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or during a write operation (CE LOW and WE LOW). To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A15). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the Truth Table on page 10 for a complete description of read and write modes. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.

Functional Description
The CY62126ESL is a high performance CMOS static RAM organized as 64K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power
Logic Block Diagram
DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
64K x 16 RAM Array
SENSE AMPS
IO0-IO7 IO8-IO15
COLUMN DECODER
BHE WE CE OE BLE
A11
A12
A13
Cypress Semiconductor Corporation Document #: 001-45076 Rev. *A
*
198 Champion Court
A14
A15
*
San Jose, CA 95134-1709
* 408-943-2600 Revised June 15, 2009
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CY62126ESL MoBL(R)
Pin Configuration
44-Pin TSOP II (Top View) [1]
A4 A3 A2 A1 A0 CE IO0 IO1 IO2 IO3 VCC VSS IO4 IO5 IO6 IO7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE IO15 IO14 IO13 IO12 VSS VCC IO11 IO10 IO9 IO8 NC A8 A9 A10 A11 NC
Product Portfolio
Power Dissipation Product Range VCC Range (V) [2] Speed (ns) Operating ICC, (mA) f = 1MHz Typ CY62126ESL Industrial 2.2V-3.6V and 4.5V-5.5V 45
[3]
f = fmax Typ [3] 11 Max 16
Standby, ISB2 (A) Typ [3] 1 Max 4
Max 2
1.3
Notes 1. NC pins are not connected on the die. 2. Datasheet specifications are not guaranteed for VCC in the range of 3.6V to 4.5V. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25C.
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CY62126ESL MoBL(R)
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Applied .............................................. 55C to +125C Supply Voltage to Ground Potential ...........................................................-0.5V to 6.0V DC Voltage Applied to Outputs in High-Z State [4, 5] ..........................................-0.5V to 6.0V DC Input Voltage [4, 5] .......................................-0.5V to 6.0V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (MIL-STD-883, Method 3015) Latch up Current..................................................... > 200 mA
Operating Range
Device CY62126ESL Range Industrial Ambient Temperature -40C to +85C VCC[6] 2.2V-3.6V, and 4.5V-5.5V
Electrical Characteristics
Over the Operating Range 45 ns Parameter VOH Description Output HIGH Voltage 2.2 < VCC < 2.7 2.7 < VCC < 3.6 4.5 < VCC < 5.5 VOL Output LOW Voltage 2.2 < VCC < 2.7 2.7 < VCC < 3.6 4.5 < VCC < 5.5 VIH Input HIGH Voltage 2.2 < VCC < 2.7 2.7 < VCC < 3.6 4.5 < VCC < 5.5 VIL Input LOW Voltage 2.2 < VCC < 2.7 2.7 < VCC < 3.6 4.5 < VCC < 5.5 IIX IOZ ICC ISB1 Input Leakage Current VCC Operating Supply Current GND < VI < VCC f = fmax = 1/tRC f = 1 MHz VCC = VCCmax IOUT = 0 mA, CMOS levels Output Leakage Current GND < VO < VCC, Output Disabled Test Conditions IOH = -0.1 mA IOH = -1.0 mA IOH = -1.0 mA IOL = 0.1 mA IOL = 2.1mA IOL = 2.1mA 1.8 2.2 2.2 -0.3 -0.3 -0.5 -1 -1 11 1.3 1 Min 2.0 2.4 2.4 0.4 0.4 0.4 VCC + 0.3 VCC + 0.3 VCC + 0.5 0.6 0.8 0.8 +1 +1 16 2.0 4 A A A mA V V V Typ [3] Max Unit V
ISB2
Automatic CE Power CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, down Current -- CMOS f = fmax (Address and Data Only), f = 0 (OE and WE), Inputs VCC = VCC(max) Automatic CE Power CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, down Current -- CMOS f = 0, VCC = VCC(max) Inputs
1
4
A
Notes 4. VIL(min) = -2.0V for pulse durations less than 20 ns. 5. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 6. Full Device AC operation assumes a minimum of 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization.
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CY62126ESL MoBL(R)
Capacitance
Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max 10 10 Unit pF pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters. Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board TSOP II 28.2 3.4 Unit C/W C/W
AC Test Loads and Waveforms
VCC OUTPUT R1 VCC 30 pF INCLUDING JIG AND SCOPE R2 GND Rise Time = 1 V/ns 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns
Equivalent to:
THEVENIN EQUIVALENT
OUTPUT Parameters R1 R2 RTH VTH 2.50V 16600 15400 8000 1.2 3.0V 1103 1554 645 1.75
RTH
V 5.0V 1800 990 639 1.77 Unit V
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CY62126ESL MoBL(R)
Data Retention Characteristics
Over the Operating Range Parameter VDR ICCDR tCDR [7] tR [8] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time CE > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V VCC = 1.5V 0 tRC Conditions Min 1.5 3 Typ [3] Max Unit V A ns ns
Data Retention Waveform
DATA RETENTION MODE VCC
VCC(min)
tCDR
VDR > 1.5V
VCC(min)
tR
CE
Notes 7. Tested initially and after any design or process changes that may affect these parameters. 8. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
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CY62126ESL MoBL(R)
Switching Characteristics
Over the Operating Range [9] Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE
[12]
Description
45 ns Min 45 45 10 45 22 5 18 10 18 0 45 22 5 18 45 35 35 0 0 35 35 25 0 18 10 Max
Unit
Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z CE LOW to Low Z
[10] [10, 11]
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
OE HIGH to High Z CE HIGH to High Z
[10] [10, 11]
CE LOW to Power Up CE HIGH to Power Up BHE / BLE LOW to Data Valid BHE / BLE LOW to Low Z
[10] [10, 11]
BHE / BLE HIGH to High Z Write Cycle Time CE LOW to Write End
Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width BHE / BLE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High Z [10, 11]
[10]
WE HIGH to Low Z
Notes 9. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" on page 4. 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 11. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output enter a high impedance state. 12. The internal write time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
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CY62126ESL MoBL(R)
Switching Waveforms
Figure 1. Read Cycle No. 1 (Address Transition Controlled) [13, 14]
tRC RC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Figure 2. Read Cycle No. 2 (OE Controlled) [14, 15]
ADDRESS
tRC CE tACE OE tDOE BHE/BLE tLZOE tHZBE tDBE tLZBE DATA OUT HIGHIMPEDANCE tLZCE tPU VCC SUPPLY CURRENT 50% 50% ICC ISB DATA VALID HIGH IMPEDANCE tHZOE tPD tHZCE
Notes 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycles. 15. Address valid before or similar to CE transition LOW.
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CY62126ESL MoBL(R)
Switching Waveforms
(continued)
Figure 3. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [16, 17]
tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA
BHE/BLE
tBW
OE DATA IO NOTE 18 tHZOE
tSD DATAIN
tHD
Figure 4. Write Cycle No. 2 (CE Controlled) [16, 17]
tWC ADDRESS tSCE CE
tSA
WE
tAW tPWE
tHA
BHE/BLE
tBW
OE tSD DATA IO NOTE 18 tHZOE DATAIN tHD
Notes 16. Data IO is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state. 18. During this period, the IOs are in output state. Do not apply input signals.
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CY62126ESL MoBL(R)
Switching Waveforms
(continued) Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW) [17]
tWC
ADDRESS tSCE CE
BHE/BLE tAW WE tSA
tBW tHA tPWE
tSD DATA IO NOTE 18 tHZWE DATAIN
tHD
tLZWE
Figure 6. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [17]
tWC ADDRESS
CE tSCE
tAW BHE/BLE tSA WE
tHZWE
tHA tBW
tPWE tSD DATAIN
tLZWE
tHD
DATA IO
NOTE 18
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CY62126ESL MoBL(R)
Truth Table
CE H X L L L L L L L L L WE X X H H H H H H L L L OE X X L L L H H H X X X BHE X H L H L L H L L H L BLE X H L L H L L H L L H Inputs/Outputs High Z High Z Data Out (IO0-IO15) Data Out (IO0-IO7); IO8-IO15 in High Z Data Out (IO8-IO15); IO0-IO7 in High Z High Z High Z High Z Data In (IO0-IO15) Data In (IO0-IO7); IO8-IO15 in High Z Data In (IO8-IO15); IO0-IO7 in High Z Mode Deselect or Power Down Output Disabled Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 45 Ordering Code CY62126ESL-45ZSXI Package Diagram Package Type Operating Range Industrial 51-85087 44-Pin TSOP II (Pb-free)
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CY62126ESL MoBL(R)
Package Diagrams
Figure 7. 44-Pin Thin Small Outline Package Type II, 51-85087
51-85087-*A
Document #: 001-45076 Rev. *A
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CY62126ESL MoBL(R)
Document History Page
Document Title: CY62126ESL MoBL(R) 1-Mbit (64K x 16) Static RAM Document Number: 001-45076 Revision ** *A ECN 2610988 2718906 Submission Date 11/21/08 06/15/2009 Orig. of Change VKN/PYRS VKN New data sheet Post to external web Description of Change
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(c) Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-45076 Rev. *A
Revised June 15, 2009
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MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. All products and company names mentioned in this document may be the trademarks of their respective holders.
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